56G per Lane SerDes

Core and analog logic may not always deploy at the same time in the same process. Maturing high performance analog typically takes longer in moving to next generation of advanced process geometries. This lagging function may slow the pace of your next generation solutions.

Credo’s unique SerDes architecture has made it possible to deliver SerDes cost & power effective solutions in mature process nodes and make them available in chip form for integration with SoCs, overcoming the need for matching core logic and SerDes IP in the same process node.

Now you can fabricate your core logic in advanced processes and combine them in your SoC with Credo SerDes Chiplets, designed for high performance and low power from mature processes. You get the performance needed without delaying your time to market.