12nm EURYTION RFK1 - UCIe SP based Ka-Ku Band Chiplet Transceiver
- UCIe based Ka/Ku band transceiver
- Wide Bandwidth
- Scalable solution for dense mm-wave radio into single multi-chip modules
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Interconnect Chiplet
- Integrates 16 complete UCIe modules, following the standard UCIe 1.1 standard
- Integrates one complete HBM3 IP, including the controller and PHY, following the HBM3 JESD238 standard
Direct Chiplet Interface
- This device will enable CrossFire customers that have integrated DCI connectivity into their Chiplets to connect to Chiplets equipped with the standard high power, low density UCIe interface.
HBM3e Advanced-packaging chiplet for all workloads
- Scalable AI, fortified with high compute density and ample memory bandwidth
High-Density Electronic-Photonic Chiplet
- Parallel electrical interface
- Supports AIB and other proprietary parallel interfaces
- 8 full-duplex optical ports
UCIe AP based 8-bit 170-Gsps Chiplet Transceiver
- 2T2R chiplet configuration
- 160/175-GSa/s sample rate
- 7-bit resolution
UCIe based 8-bit 48-Gsps Transceiver
- 48-Gsps peak sample rate
- 8 bit resolution
- UCIe SP (16x lanes at 16Gbps) with streaming controller
UCIe based 12-bit 12-Gsps Transceiver
- 12-Gsps peak sample rate
- 12 bit resolution (programmable)
- UCIe SP (16x lanes at 16Gbps) with streaming controller
Parallel Single Mode (PSM) 16-channel 112 Gbps Transmitter Chiplet
- 16x DR4 specification compliant transmit channels including modulator and driver
- Digital SPI control interface
Active silicon interposer
- Network-On-Interposer
- 4 Tbps aggregate bisection bandwidth
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Recent News
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STAMP-2.5D: Structural and Thermal Aware Methodology for Placement in 2.5D Integration
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Siemens expands OSAT Alliance membership to build domestic semiconductor supply chains
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Marvell Delivers Advanced Packaging Platform for Custom AI Accelerators
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Executive Outlook: Chiplets, 3D-ICs, and AI
2025-05-29T12:06:00+02:00
AMD Acquires Enosemi to Accelerate Co-Packaged Optics Innovation for AI Systems
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Research & Development
OSAT
Siemens expands OSAT Alliance membership to build domestic semiconductor supply chains
2025-05-30T08:27:00+02:00
Chiplet
Marvell Delivers Advanced Packaging Platform for Custom AI Accelerators
2025-05-29T15:30:00+02:00
Commentary / Analysis
Executive Outlook: Chiplets, 3D-ICs, and AI
2025-05-29T12:06:00+02:00
Business
AMD Acquires Enosemi to Accelerate Co-Packaged Optics Innovation for AI Systems
2025-05-29T08:16:00+02:00
OSAT
Business
Research & Development
Equipment
EV Group Brings Digital Lithography to Heterogeneous Integration HVM Applications with LITHOSCALE® XT
2025-05-26T12:44:00+02:00
Commentary / Analysis
Five workflows for tackling heterogeneous integration of chiplets for 2.5D/3D
2025-05-26T11:32:00+02:00
Commentary / Analysis
Advanced Packaging Depends On Materials And Co-Design
2025-05-26T09:59:00+02:00
Commentary / Analysis
ITF World 2025: Imec’s Vision for Automotive Over the Long Haul
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Chiplet
Event
Powering AI with Chiplet Innovation: MSquare's ML100 IO Die Live at COMPUTEX 2025
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Commentary / Analysis
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Commentary / Analysis
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Equipment
Deca Announces Agreement with IBM to Bring High-Density Fan-Out Interposer Production to North America
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Equipment
AEM Expands Access to Production-Proven SLT and Burn-In Ecosystem for Advanced Computing Customers
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Foundries
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Commentary / Analysis
More Data, More Redundant Interconnects
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Commentary / Analysis
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Business
Marvell and NVIDIA to Provide Custom Solutions for Advanced AI Infrastructure
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Business
Alchip Among the First with NVIDIA NVLink Fusion Design Infrastructure
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Commentary / Analysis
Development Flows For Chiplets
2025-05-15T11:00:00+02:00
Commentary / Analysis
Die-to-die Interconnect Standards In Flux
2025-05-15T10:52:00+02:00
IP
Secafy Licenses Menta's eFPGA IP to Power Chiplet-Based Secure Semiconductor Designs
2025-05-14T14:51:00+02:00
Event
Business
Avicena Announces Series B Funding Round Led by Tiger Global with Participation from SK hynix
2025-05-14T12:08:00+02:00
Business
Intel Unveils Chiplet Alliance To Enable New Chip Designs
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Commentary / Analysis
Technical Papers
Enhancing Test Efficiency through Automated ATPG-Aware Lightweight Scan Instrumentation
June 2, 2025
Modeling Chiplet-to-Chiplet (C2C) Communication for Chiplet-based Co-Design
June 2, 2025
Die-Level Transformation of 2D Shuttle Chips into 3D-IC for Advanced Rapid Prototyping using Meta Bonding
May 22, 2025
STAMP-2.5D: Structural and Thermal Aware Methodology for Placement in 2.5D Integration
May 15, 2025