• Technical Conference:  30 March – 03 April 2025
  • Exhibition: 01 – 03 April 2025
  • Moscone Center, San Francisco, California, USA

Advanced Packaging and Integrated Optics for Scale-Up AI interconnects

Wednesday, 02 April, 14:00 – 18:30

Rooms 201-202 (Level 2)

Artificial Intelligence (AI) has been driving development of state-of-art semiconductor technology within compute, memory, storage and networking domains over the last several years. Most recently however, Generative AI (Gen AI) applications, such as ChatGPT and Sora, have provided a massive impetus to the demands for computational power. Specifically, the scaling up of GPU (Graphics Processing Unit) clusters faces challenges in bandwidth density and reach. Electrical interconnects and SERDES technology are starting to run out of steam as GPU and switch die-edge bandwidth densities surge past 1 Tbits per second/mm (Tbps/mm). The number of GPUs per cluster is also growing, which begs for cluster interconnect to span multiple racks at reasonable power levels. The large impact of distance to the energy and latency of electrical interconnects is a significant impediment to scaling up.  

This symposium focuses on the widespread efforts across industry and academia to bring the optical transceiver technology, which is now ubiquitous in the datacenters, closer to the compute chips. These efforts are either in the form of Co-Packaged Optics (CPO) or Optical IO, which bring the Photonics even closer to the chip using  Advanced 2.5-3D Packaging technologies.

The symposium will be split into two sessions.

  • The first session will be kicked off with an introduction to the existing solutions and their limitations vis-à-vis the diverse application scenarios (training vs. inference, B2B vs. B2C, etc.). This will motivate the required metrics to compare different optical architectures (wide and slow, vs. fast and narrow) and optical platforms (Single vs. multi-mode, VCSELs vs. Silicon Photonics, 2D vs. 2.5D vs. 3D packaging platforms).
  • The second session will dig into the pros and cons of the different optical architecture and platform choices. It will delve into the choices of external vs. internal lasers, ring vs. Mach-Zehnder modulators, optical packaging options and all associated ecosystem developments from foundry to OSATs. It will further address considerations for system integration into GPU servers, such as associated thermal management tradeoffs, and reliability and serviceability requirements.

The format of the symposium will encompass sufficient time for open discussions as the industry navigates this multi-dimensional and multi-physics effort.

Session I
Karl Bois, NVIDIA, USA
“The Copper Behind Blackwell”: Understanding Today's Copper Scale-up Networks

Vivek Raghuraman, Mixx Technologies Inc, USA
The Paradigm Shift: Bringing Optics to AI

Julie Eng, Coherent, USA
Optical Solutions for Scale Up

Sylvie Menezo, SCINTIL Photonics, France
Integrated Versus External Laser Sources in Pluggable and Co-Packaged Optics Applications

Panel

Session II
Peter O’Brien, Tyndall, Ireland
Photonic and Electronic Co-Packaging Technologies – From Research to Pilot Manufacturing

Darrell Childers, US Conec Ltd, USA
Critical Challenges and Design Choices in Massively Parallel Optical Links

Hesham Taha, Teramount Ltd, Israel
Scalable Detachable Fiber Connectivity for Seamless Integration with Advanced Semiconductor Packaging

Y.P. Wang, SPIL, Taiwan
Advanced Packaging Solution for Co-Packaged Optics

Noam Ophir, Jabil, USA
CPO Challenges at the Contract Manufacturer (CM) and Electronics Manufacturing Services (EMS) Level

Panel

 

Speakers

Karl Bois, NVIDIA, United States

“The Copper Behind Blackwell”: Understanding Today's Copper Scale-up Networks

This presentation will delve into leading-edge copper scale-up architectures. The historical trend of bandwidth in NVIDIA GPUs and all-to-all GPU domain will be discussed. A scale-up copper architecture utilizing state-of-the-art signaling at 200 Gbit/s per differential pair will be presented, specifically the GB200 NVL 72 rack-scale design. The discussion will cover its constitutive components, including GB200 compute nodes, NVLink switch trays, and copper cable backplane cartridges.

About Karl Bois:

Dr. Karl Bois is Principal Server Connectivity Architect in the System Products Team at NVIDIA. He collaborates across many disciplines in NVIDIA engineering to drive interconnect requirements of system architectures from chip packages outward into the datacenter. He is an active participant in IEEE 802.3 and OIF, where is currently Technical Committee Chair. He is a contributor to PCIe 4.0, 5.0 and 6.0 Base Specifications. Karl holds a BSEE and MSEE from Université Laval, in Québec City (Canada) and a PhD in Electrical and Computer Engineering from Colorado State University, Fort Collins, CO. He holds over 50 U.S. Patents and authored several journal publications, proceedings, and specifications.


Darrell Childers, US Conec Ltd, United States

Critical Challenges and Design Choices in Massively Parallel Optical Links

Currently, multifiber ferrules are extremely precise optomechanical devices that achieve submicron lateral alignment and physical contact. Greatly increasing the fiber count in ferrules will pose significant challenges, necessitating compromises in both connector performance and functionality.

About Darrell Childers:

Darrell Childers received his Bachelors of Science degree in Mechanical Engineering from Georgia Institute of Technology in 1991 and his Master of Science in Mechanical Engineering from Oklahoma State University in 1996.  He joined Siecor Corporation in 1996.  He focuses primarily on the research and development of fiber optic connectors and transceiver components.  He joined US Conec in 2001 and is currently the Vice President of Research, Development, and Engineering for US Conec.


Julie Eng, Coherent, United States

Optical Solutions for Scale Up

This talk will review optical solutions for scale up, including shortwave multi-mode VCSEL-based solutions, and Silicon Photonics-based solutions including InP lasers. The state of the art including strengths and weaknesses of each path will be reviewed.

About Julie Eng:

Julie Sheridan Eng was named Chief Technology Officer (CTO) of Coherent in 2022. Prior to becoming CTO, Dr. Eng served as Senior Vice President and General Manager of Coherent/II-VI’s Optoelectronic Devices and Modules Business Unit. In that role, she oversaw engineering, product management, and operations for GaAs vertical-cavity surface-emitting lasers (VCSELs), InP directly modulated lasers (DMLs) and detectors, and CMOS/BiCMOS integrated circuits for datacom and 3D sensing applications. In particular, Dr. Eng managed GaAs VCSELs and InP lasers and detectors for consumer applications from inception to ramp to revenue. Teams she managed brought up a new 6” GaAs fabrication facility, and ramped VCSELs and InP devices for high volume consumer applications.

Dr. Eng joined Coherent/II-VI in 2018 via the II-VI acquisition of Finisar. She held various senior management positions at Finisar since joining the company in 2003, including Executive Vice President and General Manager of 3D Sensing, and Executive Vice President of Datacom Engineering. Over the 15 years she managed Datacom and Transceiver Engineering, teams she managed released hundreds of fiber optic transceiver products to manufacture and demonstrated numerous industry firsts. Prior to joining Finisar, Dr. Eng was part of AT&T/Lucent/Agere, where she managed datacom transceivers.

Dr. Eng is a Past Chair of the IEEE Committee on Women in Engineering and presently serves on the Board of Directors of Optica (formerly the Optical Society of America). She has published over a dozen papers, co-authored a book chapter, holds six U.S. patents, and has given numerous invited talks. She holds a B.A. degree summa cum laude in Physics from Bryn Mawr College and a B.S. degree in Electrical Engineering with honors from the California Institute of Technology (Caltech). She earned M.S. and Ph.D. degrees in Electrical Engineering from Stanford University. She is a Fellow of Optica and a member of the National Academy of Engineering.


Sylvie Menezo, SCINTIL Photonics, France

Integrated Versus External Laser Sources in Pluggable and Co-Packaged Optics Applications

Silicon Photonics with monolithic integrated lasers has achieved proven maturity and robustness while being manufactured in commercial CMOS foundries with advanced semiconductor packaging capabilities. DWDM optical transmissions are being made possible for ultra-high volume uncooled applications thanks to best-in-class DFB lasers produced from such technologies. We will evaluate the advantages and disadvantages of integrated laser sources on silicon: performance, power consumption, thermal aspects, ease/cost of implementation will be discussed for pluggable and co-packaged optics applications.

About Sylvie Menezo:

Sylvie Menezo is CTO of SCINTIL Photonics (France, Canada, USA), which she founded in November 2018 from CEA-Leti and drove as the CEO until December 2024. SCINTIL has developed and operates proprietary photonic technology enabling the monolithic integration of lasers on advanced silicon photonic wafers. The company focuses on the exploitation of two products fabricated from commercial foundries: arrays of multiplexed DWDM DFB lasers used as “External Laser Sources” for co-packaged optics and transceiver circuits with integrated lasers. Before, Menezo led the Silicon Photonics Lab and Business Development activities at CEA-Leti (2010-2017, France). She previously introduced, developed and led fiber optic technologies at Sercel-Compagnie Générale de Géophysique (2001-2009, France and USA), contributed to the development of PN-BH pump laser processes at Alcatel (1999-2001, France), developed disruptive multi-wavelengths laser sources for submarine communications during her PhD. (1997-1999) at CNET (1997-1999, France) and developed polymer-modulators at NZAT (1996, USA).

Since 2021, Menezo has served on the board of directors of ePIXfab.

She is involved in the technical committees of OFC, ECOC.

Sylvie Menezo holds an engineering degree from INSA Lyon (1997), a Ph.D. from CNET Bagneux (1999) and a Part Time Executive MBA from Audencia Nantes (2007).


Peter O’Brien, Tyndall, Ireland

Photonic and Electronic Co-Packaging Technologies – From Research to Pilot Manufacturing

This talk will present developments in co-packaging technologies and the transition from research to pilot-scale manufacturing. Areas to be covered include developments in glass-based electrical interposers, BGA-style photonic-electronic packages, and micro-optics for surface pluggable optical fibre connections. The talk will also review the critical role of packaging equipment in determining package designs to ensure manufacturability and emerging packaging trends in co-packaged optics.

About Peter O’Brien:

Prof. Peter O'Brien is head of the Photonics Packaging & Systems Integration Group at the Tyndall Institute, University College Cork. He is director of the European Photonics Pilot Line (www.pixapp.eu) and the European Photonics Academy (www.photonhub.eu). His group is involved in multiple EU, SFI, NSF, DARPA, and direct industry projects. Prof. O'Brien previously founded and was CEO of a start-up company manufacturing speciality photonic systems for biomedical applications, which he sold in 2009. He was a post-doctoral scholar at the California Institute of Technology and a research scientist at NASA's Jet Propulsion Laboratory, where he was involved in developing submillimetre wave devices for remote sensing applications. He received his degree and PhD in Physics from Trinity College Dublin and University College Cork respectively.


Noam Ophir, Jabil, United States

CPO Challenges at the Contract Manufacturer (CM) and Electronics Manufacturing Services (EMS) Level

CPO presents unique challenges for advanced packaging compared to traditional transceiver architectures. This talk will touch on some of those unique considerations and focus on the challenges the CM / EMS businesses are working to overcome to enable commercialization of this new class of photonics solutions.

About Noam Ophir:

Noam Ophir is a Senior Technical Director in Jabil’s Intelligent Infrastructure CTO organization, focused on advanced packaging for Silicon Photonic applications. His interests lie in tackling fundamental technical challenges facing the photonics industry, and enabling a faster / lower risk path for productization of photonic devices and systems.

He previously stood up Elenion Technologies’ (later acquired by Nokia) test infrastructure and led its test department to successful PDK standup and productization of several generations of coherent Silicon Photonic optical engines. He subsequently joined Luminous Technologies, where he took a step back from management to focus on photonic device design and modeling, before joining Jabil in 2023.

Noam received his PhD in 2012 from Columbia University where he did his research in Prof Keren Bergman’s group.


Vivek Raghuraman, Mixx Technologies Inc., United States

The Paradigm Shift: Bringing Optics to AI

AI scale-up requires high-density interconnects matching the D2D interface bandwidth. By doubling bandwidth yearly, packaging architecture changes have become unsustainable. Silicon photonics enables scaling while maintaining consistency in packaging, providing a reliable platform for generations.

About Vivek Raghuraman:

Vivek is the co-founder and CEO of Mixx Technologies, a deep-tech startup pioneering high-density interconnects for AI and high-performance computing. With over 20 years in the semiconductor industry, he’s launched groundbreaking products, including the first co-packaged optics at Broadcom and a silicon photonics transceiver at Intel. Holding seven patents, Vivek is an internationally recognized expert in silicon photonics and advanced packaging, advising the AIM leadership council, IEEE steering committee for photonics, the India Semiconductor Mission, and the Semiconductor Research Council's MAPT program, shaping the future of semiconductor technologies.


Hesham Taha, Teramount Ltd, Israel

Scalable Detachable Fiber Connectivity for Seamless Integration with Advanced Semiconductor Packaging

As the demand for high-speed, low-latency, and low-power data transfer grows in AI, high-performance computing, and data centers, optical interconnects are essential for scaling future generations of computing infrastructure. However, widespread adoption is limited by the complexities of fiber-to-photonics packaging in advanced 2.5D and 3D semiconductor architectures.

Teramount addresses these challenges through incorporation of wafer-level processes, including its Photonic-Bump and Photonic-Plug technology, which seamlessly aligns photonics packaging with standard semiconductor manufacturing and packaging flows. This approach enables large assembly tolerances, passive fiber attachment, and detachable mechanical connectivity, significantly improving yield, reworkability, and cost efficiency. The result is scalable, high-volume manufacturing that integrates fiber attachment processes into the highly demanding packaging requirements of advanced semiconductor packages.

This presentation will highlight Teramount's technological advances in wafer-level optics and integration workflows into standard semiconductor foundry and outsourced semiconductor assembly and tests (OSATs) processes. We will discuss how our innovations provide compatibility with advanced 2.5D and 3D packaging architectures, enabling post-reflow fiber attach, integration into thinned silicon photonic dies with TSVs, thin form factor support, and multiple testing points during the packaging process. These advancements are essential for driving the industry towards scalable, high-yield optical interconnects, unlocking the potential for large-scale deployment of AI and advanced computing systems.

About Hesham Taha:

Hesham Taha is CEO and co-founder of Teramount Ltd. Hesham has a PhD in Applied Physics from the Hebrew University of Jerusalem with focus on photonics, nano-microscopy and nano-lithography.


Y. P. Wang, SPIL, Taiwan

Advanced Packaging Solution for Co-Packaged Optics

As demand of generative AI growing in unprecedented speed, data processing in low latency, high bandwidth, high performance and large memory capacity is a crucial factor. Cluster computing with enormous chips is required to complete task either on the training or inference for large language models. However,  those changes would bring more power consumptions, heat dissipation problems and result in the consequence of additional overhead expenses and environmental impacts for enterprises. By enabling the chiplet and Co-Packaged Optics technology, these influences could be migrated with higher energy efficiency benefit. In this presentation, broad overview of advanced packaging and its own applications will be introduced. Recent developments on optical engine with Fan-out advanced package and integrated to Co-Packaged Optics will be discussed. In addition, challenges and solutions will be reviewed in several aspects such as design, thermal, warpage and electrical.

About Y. P. Wang:

Vice President, R&D Center, SPIL

Yu-Po Wang received Ph.D. in Mechanical Engineering from Binghamton University, State University of New York , U.S.A.

In 1997, he started career at Gintic Institute of Manufacturing Technology in Singapore.

He joins SPIL in 1998 and leads the R&D Package Application and Technology Support Team in substrate/package design, material characterization and advanced package.

Dr. Wang has strong knowledge and experience in packaging characterization including thermal/ electrical simulation, advanced material(co-development), design and advanced packaging development. He has over 83 patents in US.

IEEE Electronics Packaging Society Board of Governors (BoG) member from 2025

IEEE Electronics Packaging Society Taipei Chapter Executive Committee from 2025