Single chiplet type versus multiple chiplet types per wafer methods
By Chetan Arvind Patil, senior product engineer, NXP USA
CMM Magazine January 5, 2024
As discussed in the previous issue, the term ‘chiplet’ has gained prominence in semiconductor design and manufacturing as a solution to some of the challenges presented by Moore's Law slowing down. Instead of integrating all functions on a monolithic die, the chiplet method disaggregates the monolithic die into smaller, modular dies or chiplets that can be manufactured separately and assembled on an interposer or package.
There are two ways in which chiplets can be manufactured: single chiplet type per wafer or multiple chiplet types per wafer.
Single chiplet type per wafer method
In the single chiplet type per wafer method, a wafer will carry one chiplet type. This means that every chiplet type has its own wafer flow.
Next, all the different wafers, each with a specific chiplet type, will follow the assembly and testing process before being assembled into a single package via heterogeneous integration. As an example, if a monolithic die is disaggregated into six chiplet types, each of the chiplet types will have its own wafer as well as fabrication, assembly and testing methods.
To read the full article, click here
Related Chiplet
- 12nm EURYTION RFK1 - UCIe SP based Ka-Ku Band Chiplet Transceiver
- Interconnect Chiplet
- Bridglets
- Automotive AI Accelerator
- Direct Chiplet Interface
Related Technical Papers
- Defect Analysis and Built-In-Self-Test for Chiplet Interconnects in Fan-out Wafer-Level Packaging
- The Survey of Chiplet-based Integrated Architecture: An EDA perspective
- Signal Integrity Challenges in Chiplet-Based Designs: Addressing Performance and Security
- Stop-For-Top IP model to replace One-Stop-Shop by 2025... and support the creation of successful Chiplet business
Latest Technical Papers
- Enhancing Test Efficiency through Automated ATPG-Aware Lightweight Scan Instrumentation
- Modeling Chiplet-to-Chiplet (C2C) Communication for Chiplet-based Co-Design
- Die-Level Transformation of 2D Shuttle Chips into 3D-IC for Advanced Rapid Prototyping using Meta Bonding
- STAMP-2.5D: Structural and Thermal Aware Methodology for Placement in 2.5D Integration
- MCMComm: Hardware-Software Co-Optimization for End-to-End Communication in Multi-Chip-Modules