TSMC drives A16, 3D process technology
By Nick Flaherty, eeNews Europe (November 20, 2024)
TSMC is looking to introduce its A16 1.6nm process by the end of 2026 with an IEEE standard for its 3Dblox technology.
The Open Innovation Platform (OIP) meeting in the Netherlands this week showed that the 2nm process will be in production in 2025 following early tapeouts this year, with a variant called N2P nanoFlex with the option for short standard cells for smaller area and greater power efficiency or tall cells for more performance.
This will give a 12% boost in energy efficiency over the base 2nm process, while A16 will give a 30% boost with the same density as N2 nanoFlex. Both TSMC and Intel are detailing their 2nm technologies at the IEDM conference in December.
To read the full article, click here
Related Chiplet
- 12nm EURYTION RFK1 - UCIe SP based Ka-Ku Band Chiplet Transceiver
- Interconnect Chiplet
- Bridglets
- Automotive AI Accelerator
- Direct Chiplet Interface
Related News
- Cadence and TSMC Advance AI and 3D-IC Chip Design with Certified Design Solutions for TSMC’s A16 and N2P Process Technologies
- TSMC to Provide 3DIC Integration for AI Chips in 2027, Featuring 12 HBM4 and Chiplets Manufactured with A16
- Ansys Strengthens Collaboration with TSMC on Advanced Node Processes Certification and 3D-IC Multiphysics Design Solutions
- Chiplet Pioneer Eliyan Achieves First Silicon in Record Time with Implementation in TSMC 5nm Process, Confirms Most Efficient Chiplet Interconnect Solution in the Multi-Die Era
Latest News
- Untether AI Enters Into a Strategic Agreement with AMD
- Alphawave Semi Tapes Out Breakthrough 36G UCIe™ IP on TSMC 2nm, Unlocking Foundational AI Platform IP on Nanosheet Processes
- How Secure Are Analog Circuits?
- Sarcina Technology advances photonic package design to address key data center challenges
- Imec demonstrates 16nm pitch Ru lines with record-low resistance obtained using a semi-damascene integration approach