Chiplet Tradeoffs And Limitations
Multi-die assemblies offer more flexibility, but figuring out the right amount of customization can have a big impact on power, performance, and cost
By Ann Mutschler, SemiEngineering | April 10th, 2025
The semiconductor industry is buzzing with the benefits of chiplets, including faster time to market, better performance, and lower power, but finding the correct balance between customization and standardization is proving to be more difficult than initially thought.
For a commercial chiplet marketplace to really take off, it requires a much deeper understanding of how chiplets behave individually and together. There needs to be a consistent way to connect chiplets to each other and to various other components, to characterize them so they can be re-used across multiple designs, and to package and test them. On top of all of that, there needs to be a way to accomplish all of this more easily at the very outset of the design process. And while this has some similarities to the soft IP market, the shift to what is essentially a collection of hardened IP requires more structural and thermal analysis, more physics, and a deeper understanding of how everything will be packaged and ultimately used.
To read the full article, click here
Related Chiplet
- 12nm EURYTION RFK1 - UCIe SP based Ka-Ku Band Chiplet Transceiver
- Interconnect Chiplet
- Bridglets
- Automotive AI Accelerator
- Direct Chiplet Interface
Related News
- DreamBig Semiconductor Announces Partnership with Samsung Foundry to Launch Chiplets for World Leading MARS Chiplet Platform on 4nm FinFET Process Technology Featuring 3D HBM Integration to Solve Scale-up and Scale-out Limitations of AI for the Masses
- Metrology And Inspection For The Chiplet Era
- Weaving State-of-the-Art Chiplet and SoC Fabrics
- The Basics of Chiplet Integration and Importance of Adhesive Solutions
Latest News
- Untether AI Enters Into a Strategic Agreement with AMD
- Alphawave Semi Tapes Out Breakthrough 36G UCIe™ IP on TSMC 2nm, Unlocking Foundational AI Platform IP on Nanosheet Processes
- How Secure Are Analog Circuits?
- Sarcina Technology advances photonic package design to address key data center challenges
- Imec demonstrates 16nm pitch Ru lines with record-low resistance obtained using a semi-damascene integration approach