Chiplet Standard Goes 3D
By Gary Hilson, EETimes (September 9, 2024)
The standards governing chiplet technology now have a second iteration.
The Universal Chiplet Interconnect Express (UCIe) Consortium, which was formed in March 2022, recently released its 2.0 specification with updates that address design challenges for testability, manageability and debug (DFx) for the SiP lifecycle across multiple chiplets. A key feature of the update is support for 3D packaging to enable chiplets to dramatically increase bandwidth density and power efficiency.
In a briefing with EE Times, consortium chair Debendra Das Sharma said that the UCIe 2.0 specification is fully backward compatible, while introducing optional manageability features and a UCIe DFx Architecture (UDA) that supports vendor agnostic chiplet interoperability.
The consortium has spread work on the specification across several working groups that focus on different aspects, including electrical, protocol, form factor and compliance, manageability and security, and systems and software. Das Sharma said a recently formed automative working group reflects an interest from that sector to start gathering requirements.
To read the full article, click here
Related Chiplet
- 12nm EURYTION RFK1 - UCIe SP based Ka-Ku Band Chiplet Transceiver
- Interconnect Chiplet
- Bridglets
- Automotive AI Accelerator
- Direct Chiplet Interface
Related News
- System-level UCIe IP for early architecture analysis of 3D Chiplet Design and Packaging
- Expanding the Chiplet Market: Processing Any Wafer from Any Foundry
- The Basics of Chiplet Integration and Importance of Adhesive Solutions
- DreamBig Semiconductor Announces Partnership with Samsung Foundry to Launch Chiplets for World Leading MARS Chiplet Platform on 4nm FinFET Process Technology Featuring 3D HBM Integration to Solve Scale-up and Scale-out Limitations of AI for the Masses
Latest News
- Untether AI Enters Into a Strategic Agreement with AMD
- Alphawave Semi Tapes Out Breakthrough 36G UCIe™ IP on TSMC 2nm, Unlocking Foundational AI Platform IP on Nanosheet Processes
- How Secure Are Analog Circuits?
- Sarcina Technology advances photonic package design to address key data center challenges
- Imec demonstrates 16nm pitch Ru lines with record-low resistance obtained using a semi-damascene integration approach