MFIT : Multi-FIdelity Thermal Modeling for 2.5D and 3D Multi-Chiplet Architectures
Abstract
Rapidly evolving artificial intelligence and machine learning applications require ever-increasing computational capabilities, while monolithic 2D design technologies approach their limits. Heterogeneous integration of smaller chiplets using a 2.5D silicon interposer and 3D packaging has emerged as a promising paradigm to address this limit and meet performance demands. These approaches offer a significant cost reduction and higher manufacturing yield than monolithic 2D integrated circuits. However, the compact arrangement and high compute density exacerbate the thermal management challenges, potentially compromising performance. Addressing these thermal modeling challenges is critical, especially as system sizes grow and different design stages require varying levels of accuracy and speed. Since no single thermal modeling technique meets all these needs, this paper introduces MFIT, a range of multi-fidelity thermal models that effectively balance accuracy and speed. These multi-fidelity models can enable efficient design space exploration and runtime thermal management. Our extensive testing on systems with 16, 36, and 64 2.5D integrated chiplets and 163 3D integrated chiplets demonstrates that these models can reduce execution times from days to mere seconds and milliseconds with negligible loss in accuracy.
I Introduction
Massive data from different modalities, including text, images, video, and speech, are continuously produced by various sensors. At the same time, increasingly complex artificial intelligence (AI) and machine learning (ML) algorithms process this data to enable new applications that were previously impractical. This trend dictates the design of large-scale chips with high memory and compute capabilities, offering a high degree of parallelism [1, 2]. Traditional 2D chip design and packaging technologies cannot sustain this need due to the low yield of large monolithic planar chips and the corresponding increase in fabrication cost [3]. Therefore, new design approaches are required to meet the increasing demand for computing power and memory capacity [1].
2.5D and 3D chiplet-based architectures have emerged as promising alternatives to traditional monolithic 2D chips due to their lower fabrication costs [4, 5, 6]. Compared to conventional monolithic systems, chiplet-based systems integrate multiple small pre-fabricated chips (chiplets) on a silicon interposer, which facilitates data exchange, as illustrated in Figure 1(a). 3D packaged systems expand on this approach by stacking multiple chiplets vertically and connecting them with vertical vias, creating a more compact system as illustrated in Figure 1(b). The smaller size of these chiplets enables a higher yield and lower overall manufacturing cost than traditional monolithic dies [7]. Additionally, this modular approach facilitates scaling the system sizes and enables heterogeneous integration of different chiplet types, e.g., memory, processing, and processing-in-memory chiplets. Hence, emerging 2.5D and 3D architectures enable a new cost-effective avenue for compact scale-out implementations of various emerging compute- and data-intensive applications, including AI/ML. Indeed, these advantages have led to industrial adoption by companies including Intel [8, 9], AMD [10, 11, 12], and NVIDIA [4].


Thermal bottlenecks have long been a significant barrier to increasing the performance of computing systems. 2.5D and 3D integrated systems exacerbate this barrier due to their dense integration and unique physical structure [13]. In contrast to a monolithic chip, where heat is spread directly across the die, a 2.5D chiplet-based system conducts heat between different chiplets through the interposer and heat spreader. Likewise, heat also flows vertically between adjacent stacked chiplets in a 3D chiplet-based system.
These factors introduce unique challenges for effective thermal management in these systems. Traditional design flows and physical floor planning focus on reducing wire lengths to meet timing constraints and minimizing area to reduce fabrication costs. However, these objectives could also lead to thermal crosstalk, thermal hotspots, and compromise performance. Chiplet-based systems introduce additional design parameters such as inter-chiplet link length, spacing, chiplet placement, sizing, inter-layer communication, and design partitioning. Tuning traditional and chiplet-based design parameters while maintaining thermal stability is critical to ensure a thermally-efficient design.

The semiconductor chip design cycle spans multiple phases: system specification, architecture exploration, logic design, physical design and validation, fabrication, and post-silicon optimization/validation. Each phase has a unique set of design constraints and requirements. For example, lacking a test chip during the pre-silicon phases requires simulation and analytical models. Finite Element Method (FEM) simulations offer the most accurate approach for pre-silicon thermal analysis [14]. They can serve as a reference and enable heat flow studies to guide the design process. However, they are too slow for practical architecture and design space exploration (DSE). Modeling the package as a thermal RC (resistive-capacitive) network can significantly accelerate simulations with acceptable accuracy loss [15, 16]. Since each node in the thermal circuit corresponds to a specific location in the package, thermal RC models solve discretized versions of the FEM models in space. Hence, they enable thermally-aware DSE and optimization with a finite number of discrete hotspot nodes. However, the thermal resistance/capacitance values and the circuit topology must accurately reflect the chip geometry and material properties for reliable results. Since the thermal RC models solve continuous-time ordinary differential equations (ODEs), they have execution times in the order of seconds to minutes. Therefore, they cannot be used for runtime optimization tasks such as dynamic thermal and power management (DTPM). One can discretize them in the time domain with a given sampling period [17, 18]. The resulting discrete state-space (DSS) models significantly reduce runtime at the cost of further abstracting the model from the physical package. Consequently, they are applicable only to the specific configurations for which they are developed.
There is a strong need for tools to accurately analyze the thermal behavior of 2.5D and 3D integrated systems and guide their design process. However, no single modeling technique can alone address the needs of all design phases. To address this much needed gap, this paper proposes MFIT, a multi-fidelity thermal modeling framework that synergistically exploits the strengths of each class of models (FEM, thermal RC, and DSS). We use this framework to produce a set of thermal models that can guide the entire design cycle, unlike a point solution that can serve a specific portion of the design process. The elements of this set not only cover complementary parts of the design cycle but support each other and produce consistent results. We first develop a fine-grained FEM model of the target package as a reference. Since it is slow and computationally expensive, we next judiciously design an abstracted version of this fine-grained FEM model to simulate an entire package in days while maintaining accuracy. To enable fast DSE, MFIT also incorporates thermal RC circuit models verified against the reference FEM models. Our thermal RC models run in the order of seconds while leading to less than 1.7∘C error, as summarized in Figure 2. Hence, they can be used for pre-silicon architectural optimization, such as mapping the workloads to chiplets, network-on-interposer design, and chiplet placement for 2.5D and 3D stacked systems. Finally, MFIT derives one more class of models by discretizing the thermal RC models, enabling runtime thermal management and large-scale DSE in the order of milliseconds. However, they work only for a specific sampling period and configuration. Hence, the parameters must be regenerated from the RC model if the target configuration changes. In summary, we obtain a set of multi-fidelity thermal models that guide and complement each other to cover all design phases.
The key contributions of this work are as follows:
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A novel thermal modeling approach that systematically abstracts fine-grained FEM models to produce abstract FEM, thermal RC, and DSS models to achieve varying speed and accuracy trade-offs,
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A family of open-source multi-fidelity thermal models that span a wide accuracy (reference to 1.7∘C) and speed (days to milliseconds) range,
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Extensive evaluations with 16, 36, and 64 - 2.5D and 163 - 3D integrated chiplets systems running AI/ML workloads to demonstrate the accuracy and speed-up benefits of our multi-fidelity thermal models,
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Open-sourced code for thermal RC and DSS models at github.com/AlishKanani/MFIT. Additionally, we plan to make our FEM models publicly accessible in the near future.
II Related Work
2.5D and 3D integration-based systems are becoming mainstream due to higher performance and lower manufacturing costs than monolithic chips. Both domain-specific and general-purpose 2.5D and 3D architectures have been explored to date [11, 19, 20, 5, 4, 21, 12]. SIMBA is one of the first prototype multi-chip modules with 36 chiplets designed for inference with deep models [4]. Similarly, Floret is a data center-scale architecture for accelerating convolutional neural network (CNN) inferencing tasks by exploiting the dataflow knowledge [5]. Loi et al., [22] analyze the performance benefits of vertically integrated (3D) processor-memory hierarchy under thermal constraints. Similarly, Eckert et al. [21] consider processing-in-memory (PIM) architectures implemented using 3D die stacking. They study the thermal constraints across different processor organizations and cooling solutions to identify viable solutions. Our proposed open-source thermal models catalyze similar thermal analysis and optimization studies for 2.5D and 3D integrated systems.
The most accurate and direct thermal evaluation approach is temperature measurements on a hardware system. It can be performed using thermal imaging [23, 24] or temperature sensors [25, 26]. However, the availability of the target hardware is a significant limitation. For example, large-scale 2.5D and 3D chiplet systems with tens of chiplets do not exist yet, while smaller prototypes and commercial systems provide limited insights applicable for larger systems [10, 27]. This limitation motivated FEM-based modeling as the most accurate way to analyze the heat flow and temperature [14]. Proprietary software, such as ANSYS Fluent [28] and COMSOL [29], are commonly used for FEM simulations. Since FEM suffers from computational cost, detailed FEM solutions are suitable only for small designs and validating analytical models [28]. For example, the authors of [30] employ FEM to simulate a two-chiplet system on an interposer. They employ abstracted FEM models for both -bumps and C4 bumps to speed up the process, effectively reducing computational complexity before tackling the entire system.
The computational overhead and impractically high execution time of FEM solvers motivate analytical models that enable rapid thermal evaluation in early design phases. The most common method involves constructing thermal RC networks and solving the corresponding system of ODEs. Popular thermal simulators such as HotSpot [15] leverage this method, focusing on the microarchitectural layout blocks to facilitate design space exploration and early-stage thermal-aware layout and placement. Similarly, 3D-ICE [16] models liquid cooling with microchannels embedded between silicon layers. PACT [31] also employs a similar methodology by utilizing SPICE tools as solvers, focusing on standard-cell-level thermal analysis for 2.5D systems. However, these tools are not fast enough for large-scale, thermally-aware DSE of multi-chiplet 2.5D and 3D integrated systems.
2.5D and 3D packages often involve materials with varying thermal conductivity across different directions. For example, the thermal conductivity of the C4 layer is higher in the vertical direction than in the lateral direction. The existing thermal models [15, 16, 31] do not account for these variations. Moreover, they assume a uniform grid size for all material layers (e.g., interposer, C4 bumps, chiplets). In contrast, the thermal RC models in our multi-fidelity set allow varying thermal conductivity across different directions and grid sizes for each layer and block.
Architecture-level thermal RC models are well-suited for offline studies, such as architectural exploration, temperature sensor placement [32, 33], and thermal-aware chiplet placement [34]. However, DTPM requires a much faster temperature estimation time, in the order of milliseconds, for real-time temperature management [18, 35]. DSS models address this need by deriving a discrete-time linear time-invariant system that models the thermal dynamics at fixed locations as a function of the power consumption. For instance, TILTS [36] discretizes the power inputs to the chip over fixed time intervals to accelerate thermal simulations. Hence, it needs to be reproduced when the timing requirements or the underlying hardware configuration change. The speedup gain offsets the loss of the explicit connection to the hardware parameters (e.g., thermal conductance and capacitance) and generality.
The results of FEM, thermal RC, or other thermal simulations can also be used to train physics-informed machine learning techniques to model heat transfer in integrated circuits to reduce the thermal modeling effort [37]. For example, a recent technique collects data from numeric simulations and trains a random forest model to predict the convection heat transfer coefficients for a nonlinear heat transfer problem [38]. Similarly, Hwang et al., [39] present closed-form models derived from numerical simulations for tapered micro-channels to analyze the heat transfer performance as a function of the channel geometry. In contrast to individual classes of thermal models, this work proposes a framework to produce a family of multi-fidelity thermal models for 2.5D and 3D chiplet-based systems. The specific set of models designed with this framework covers a wide range of accuracy and execution time trade-offs, making them suitable for different design phases. Additionally, they can be augmented by additional models, such as physics-informed ML models, with complementary accuracy and execution time trade-offs.

III FEM for Thermal Analysis
FEM analysis begins by dividing the problem domain into small finite elements, converting the continuous governing partial differential equations (PDEs) into algebraic equations. Next, the system’s geometry is broken down into a lattice of small discrete cells called a “mesh” which approximates a larger, continuous block [28]. After applying the PDEs and boundary conditions to each element, the equations are assembled into a global algebraic system, maintaining continuity between adjacent elements. This global system, representing the discretized PDEs over the whole domain, is solved numerically for the field variables at each mesh node. In this work, only the equation governing solid conduction is solved [14]:
(1) |
where is the thermal conductivity, is the temperature, is the heat generation rate, is the density, and is the volumetric specific heat.
III-A Stages of the FEM Simulation Pipeline
Performing FEM simulations involves several key processing steps visualized in Figure 3. First, the geometry, a 3D representation of the 2.5D or 3D integrated package, is created using computer-aided design tools. This geometry should be as detailed as possible while allowing the setup and simulation to be completed within the given time constraints. Next, a volumetric mesh is generated by transforming the 3D model into one consisting of many individual cells on which the FEM software operates. This step can be iterated since creating appropriate mesh (aka meshing) is critical for computation time and accuracy of solutions. Once an acceptable mesh has been created, it is imported into the solver. The simulation is then set up, including boundary conditions, material parameters, power source terms, and other general model parameters. Our specific system setup is expanded upon in Section V. Finally, the FEM software simulates the model by solving the governing heat transfer equations.
III-B Impracticality of FEM Simulations
While FEM simulations offer high accuracy, they are impractical for DSE or runtime thermal management due to their time-consuming setup and operation. The process of geometry creation, meshing, solver setup, and execution is intricate and often exceeds the simulation runtime itself. Because the simulation process requires multiple iterations for reliable results, this time overhead quickly becomes prohibitive. The setup of 2.5D or 3D integrated systems is especially complex due to the large number of discrete power sources. These systems also involve numerous small and large bodies, dramatically increasing the computational complexity and the solver runtime [28]. Simulation times range from hours to days, directly impacted by geometric detail, complexity, size, and setup parameters such as the time step. Consequently, analyzing 2.5D or 3D integrated systems with intricate geometries and operating conditions using FEM simulations becomes prohibitively time-consuming, highlighting the need for alternative approaches.



IV Multi-Fidelity Thermal Modeling
IV-A Overview of the Proposed Approach
Our multi-fidelity thermal model set involves four individual models, visualized in Figure 4. The process of creating these models is identical to any packaging technology. MFIT considers 2.5D chiplet on silicon interposers and 3D direct bonded systems [9].
We start by creating fine-grained FEM models of specific components within the package. For example, we model individual links within the interposer and -bumps connecting a chiplet to the interposer. The cost of this level of detail is the model complexity and execution times that limit the simulation scope. Therefore, the fine-grained models are used as a reference to design abstracted FEM models, as explained in the following subsection. This abstraction enables system-level FEM simulations of systems with much higher chiplet counts than would otherwise be possible with negligible accuracy loss. The third class in the MFIT framework is the thermal RC models. Since these models are constructed using the geometry and material parameters of the system, a new RC model of a different system configuration can be created without re-running FEM simulations, allowing for rapid DSE. Finally, the continuous-time state-space equations that govern the thermal RC models are discretized with a given sampling period to create DSS models as detailed in Section IV-D.
IV-B Fine-Grained to Abstracted FEM Modeling
First, fine-grained models of key system components are constructed with as much detail as possible. Fine-grained modeling of the entire system at the highest level of detail is infeasible due to the memory, CPU, and execution time requirements. The second step is systematically designing abstracted models by replacing detailed structures with homogeneous blocks. During this process, we find the material parameters for these blocks such that their thermal behavior matches the original structure.
MFIT focuses on two structures within a chiplet-based package for this work: the -bumps connecting each chiplet to the interposer and the links that enable communication between chiplets. The rationale behind selecting these components is elaborated on in the following subsections. These two structures are present in both 2.5D and 3D chiplet-based packages, as shown in Figures 5 and 6, and the results of the abstraction experiments are applied to both the 2.5D and 3D full-system abstracted models.
While we apply our abstract modeling approach to only two structures in this work, the same approach applies to other structures in the package, such as the substrate or C4 bumps. In addition to these abstractions, MFIT also models the heatsink as a heat transfer coefficient (HTC) instead of a physical model. This choice removes the need to model fluids in our simulations, as fluid flow is only used for convective heat transfer in the heatsink.
To capture the 3D chiplet-based systems, we consider direct die-to-die bonding between vertically stacked chiplets as an example. With this bonding method, no additional layers are modeled between stacked chiplets. Instead, chiplets are modeled directly contacting each other, stacked one on top of the other. Similarly, another bonding method can be utilized, such as TSVs or -bumps between stacked chiplets. When modeling the geometry of TSVs or -bumps between stacked chiplets in a system, an additional block of homogeneous material is created between each stacked chiplet. This block has the same thickness as the thickness of the bonding method. Then, to determine the material parameters of this new block, an identical process is followed to that described in the following section.
IV-B1 -bump Abstracted Model
The -bumps are particularly important for thermal behavior since they are one of the two paths to dissipate heat away from a chiplet, as seen in Figure 5. Due to the density and the total number of -bumps present, which number in the thousands, it is impractical to simulate an entire package with individually modeled -bumps. Therefore, a small block of the -bump layer, along with the associated chiplet and interposer, is simulated in isolation to determine thermal coefficients that can be applied to the final abstract models as illustrated in Figure 7.

First, the detailed block containing -bumps and underfill material is simulated with static heat and convection boundaries, which are applied to create a measurable thermal gradient across the -bump layer. Then, the thermal conductivity is calculated as:
(2) |
where is the heat flow rate, is the thickness of the material, is the cross-sectional area, and is the temperature difference across the material [40]. Thermal capacitance and specific heat are calculated via weighted body average [41]. These parameters are applied to a model containing a homogeneous block in place of the previously modeled -bumps and underfill material. Finally, the same boundary conditions are used, as shown in Figure 7.
We observe identical temperature drop across the -bump layer of the abstracted model and less than a tenth of a degree difference in interface temperatures in this sub-block, as presented in Table I, while achieving approximately 1.5x speedup.
Model |
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Detailed -bumps | 39.13 | 31.05 | 8.08 | ||||||
Abstracted -bumps | 39.26 | 31.18 | 8.08 |
IV-B2 Link Abstracted Model
A link is a group of wires embedded in the interposer to interconnect chiplets. Depending on the thermal crosstalk over the links, the NoI architecture can play a significant role in a system’s thermal behavior. To determine how links are modeled in the complete system simulations, we tested three different configurations of a two-chiplet package. These configurations model the link (1) in full detail, (2) as an abstracted block, and (3) not model at all. We use two different power configurations: (a) the power dissipation is static over time, and (b) it varies dynamically over time. These power consumption profiles are applied to one chiplet while the temperature of the other chiplet is calculated through FEM simulation. The mean absolute error (MAE) of the receiving chiplet temperature compared to the detailed model case is recorded in Table II. Only a minimal accuracy loss is observed for both cases, while execution time savings are significant, as shown in Table III. Therefore, we choose not to model links in our full-system simulations.
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Abstracted links | 0.05 | 0.02 | |||||
No links | 0.34 | 0.13 |
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Detailed links | 489.23 | 503.86 | |||||
Abstract links | 164.29 | 172.64 | |||||
No links | 123.80 | 132.13 |
IV-B3 Heatsink Abstracted Model
FEM simulations that involve a heatsink must model the convective heat transfer from the heatsink to the atmosphere using fluid models [30]. However, modeling fluid dramatically increases the setup and simulation time. Additionally, the geometry must be modified for every heatsink configuration, further increasing the time needed for design iteration. Due to their complexity, high-performance cooling methods, such as liquid cooling, are also difficult to model in FEM-based simulations.
MFIT removes the need to model the heatsink by abstracting the cooling solution to a single HTC. We then apply this coefficient to the top of the lid where a heatsink would typically sit. Modeling a heatsink as an HTC is an active area of research that has been studied for many different cooling solutions [42, 43]. This approach allows for a great deal of flexibility in FEM modeling. Instead of completing the time-consuming pipeline in Figure 3, the HTC can be modified to test the behavior of different cooling solutions.
MFIT, assumes an active air-cooled heatsink. The value of the HTC of an air-cooled heatsink is determined by:
(3) |
where is the total area of the heatsink, is the fin area, is the number of fins, is the fin efficiency, and and are the length and width of the base plate. While the average convective HTC () can be calculated using the Nusselt number [41]. We select values consistent with a basic copper heatsink with forced airflow provided by a typical commercial computer fan. The parameters can be easily tuned to reflect different cooling solutions. Applying this method accelerates the simulation process substantially.
While this method is effective for systems where heat is dissipated primarily through the lid, a different approach may be required for other cooling methods, such as inter-tier liquid cooling, where microchannels contact the chip directly [39, 38]. In such an approach, heat is dissipated directly from the chip without moving to a heat spreader like the lid. Hence, additional heat transfer coefficients or abstraction techniques may be needed to capture the cooling behavior.
IV-C FEM to Thermal RC models
Notation | Definition |
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,, | Thermal conductivity of a layer along the x, y, and z axes |
,, | Thermal conductance of a node along the x, y, and z axes |
Material density | |
Volumetric specific heat of a layer | |
Convection conductance of a boundary node | |
Heat transfer coefficient of heatsink | |
N | Total number of nodes in the RC and DSS models |
Nx1 temperature matrix and its derivative | |
Nx1 matrix of heat generation | |
NxN thermal capacitance and conductance matrices |
This section describes the process of constructing a thermal RC model from the geometry of a given package. MFIT applies this technique to both 2.D and 3D systems demonstrating the flexibility of the proposed methodology to different packaging technologies. However, this process can easily be applied to any package.
The package is first divided into horizontal layers, with the slicing process starting at the bottom substrate layer and ending at the top lid layer. Depending on the package design, each layer may be composed of uniform material or various material blocks. This flexibility enables the thermal RC model to simulate packages with heterogeneous designs where different chiplets are manufactured with various technologies, resulting in different material parameters in the same layer. For layers with uniform material properties, it is divided into a 2D grid of nodes. When a layer contains different material blocks, each block can be divided into grids with different levels of granularity. a 3D network of thermal nodes that discretizes the chiplet geometry in space.
Since a layer or material blocks may have anisotropic material, where thermal conductivity differs along the x, y, and z axes (represented by , , and ), we calculate the thermal conductance (, , ) for each node using the following equations:
(4) |
where and are the node lengths in the x and y dimensions, respectively, and represents the thickness of the layer. The thermal capacitance of each node is then calculated as , where is material density and is the volumetric specific heat.
Heat is dissipated from the package primarily through a heatsink which is simulated using a convective heat transfer coefficient as detailed in Section IV-B3. MFIT assumes forced convection is applied to the heatsink while passive convection occurs on the other external boundaries of the package. Consequently, convective conductance () is incorporated into the nodes of the top and bottom layers.
The conductance between neighboring nodes and () of the same layers is determined by lateral conductances ( and ). Unlike existing thermal RC models [44, 16, 31], our thermal RC model allows non-uniform grid sizes for different layers and blocks, so a node in one layer can be connected to multiple nodes from adjacent layers. Thus, vertical conductances between nodes of different layers are calculated from , considering the overlap in the x-y plane. Once this RC network is established, we can formulate an ODE based on Kirchhoff’s current law for a node as:
(5) |
The heat generation () from node is analogous to electric current, and temperature () is analogous to voltage. Since only the chiplet layers consume power, heat generation for the nodes in other layers is zero. Solving the system of ODEs by forming a matrix is a well-studied approach. It can be represented by:
(6) |
where , , and are matrices representing node temperatures, temperature derivative, and generated heat. is a diagonal matrix, where each element corresponds to a node’s thermal capacitance. The conductance matrix can be expressed as:
(7) |
where, represents conductance between the neighboring nodes and .
MFIT employs the highly adaptive solver LSODA [45] to solve this system of ODEs. LSODA is designed to handle both stiff and non-stiff systems efficiently. It dynamically switches between different numerical integration methods depending on the characteristics of the ODE system being solved. This switching capability is particularly useful for thermal ODEs, as the equations’ stiffness can vary over time depending on the power consumption. It is worth noting that the matrices representing the system are highly sparse since each node is connected to only a few neighboring nodes. MFIT leverages this sparsity to accelerate the solver’s execution time. Finally, we fine-tune the capacitance values of each layer utilizing FEM results as a reference to improve the accuracy of our model.
IV-D Thermal RC to Discrete State Space models
The thermal RC model can be discretized in the time domain to further reduce the execution time of the model with no cost of accuracy. The resulting DSS model’s limitation is its dependence on an underlying continuous time model. It cannot be constructed directly without a thermal RC model as an intermediate step or system identification and measurement data. Additionally, a DSS model is specific to the geometry, materials, and sampling period used during the creation of the thermal RC model and the later discretization process. Therefore, the DSS model must be reconstructed if any design parameter changes. Only an existing RC model and a set time step are required to create a DSS model, with no direct information from the previous FEM model being needed.
Integrating the continuous time system, as given in Equation 6 for results in [46]:
(8) |
Assuming constant heat generation during the sampling period , the system can be discretized from continuous time variable to discrete steps as:
(9) |
where and are the state and input matrices. Equation 9 represents the discrete-time equivalent of the continuous-time thermal RC model (shown in Equation 6). MFIT uses the zero-order hold (ZOH) method for the discretization process. When power is provided as discrete inputs at each sampling period, ZOH provides an exact match to the continuous time model. can be determined for discretization as a function of input power consumption and system dynamics.
DSS model consists only of multiply-accumulate operations, allowing for extremely fast operation, as shown in Section V. The discretization process is also nearly instantaneous, allowing for rapid DSS model creation when a thermal RC model is available.
V Experimental Results
V-A Experimental Setup
We evaluate the accuracy of the proposed MFIT methodology on three 2.5D systems and one 3D system representative of their respective classes. Three separate 2.5D systems are studied to demonstrate the flexibility of the proposed approach for systems with different numbers of chiplets. A 3D system is considered to demonstrate the capability of the approach to model systems beyond a single planar layer of chiplets. Our thermal RC and DSS models are open-sourced to catalyze research in this domain. The rest of this section describes the parameters and geometry of the 2.5D and 3D systems considered in this paper.
Parameter | 16 2.5D | 36 2.5D | 64 2.5D | 16x3 3D | ||
Package Geometry | ||||||
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1.855 | 1.855 | 1.855 | 2.255 | ||
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15.5 | 21.5 | 27.5 | 15.5 | ||
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240.25 | 462.25 | 756.25 | 240.25 | ||
Package Volume (mm3) | 445.66 | 857.47 | 1402.84 | 534.55 | ||
Power (100% utilization) | ||||||
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3 | 3 | 3 | 1.2 | ||
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48 | 108 | 192 | 57.6 | ||
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0.199 | 0.233 | 0.253 | 0.239 | ||
Temperature | ||||||
|
118.25 | 129.75 | 164.03 | 128.65 |
V-A1 Package Overview
Both the 2.5D and 3D systems utilize a silicon interposer with chiplets placed upon it. The interposer is connected to the underlying substrate using C4 bumps. Copper wires embedded in the interposer are used to connect neighboring chiplets. In both our 2.5D and 3D systems, each chiplet area is considered to be , consistent with prior studies [19, 20, 5]. Each chiplet consists of multiple blocks. Each of these blocks corresponds to a component such as a computational tile or a router used for inter-chiplet communication, as detailed in Figure 1(a). Each of these blocks which make up the chiplet has an individual power profile. This means that different power profiles can be applied to every computational tile and router port in each chiplet. In our experimentation, different levels of detail are applied to the chiplets in the 2.5D and 3D system, as described in the following sections.
2.5D System Specifics: The target 2.5D system consists of a grid of chiplets integrated on an interposer, as illustrated in Figure 1(a). Each chiplet is connected directly to the interposer via -bumps surrounded by a capillary underfill material. The physical dimensions of the router ports are compatible with Universal Chiplet Interconnect Express (UCIe) specification [47]. The entire package is covered by a copper lid, which contacts each chiplet through a thermal interface material (TIM).
3D System Specifics: In the 3D system, three stacked chiplets are placed in a 4x4 grid with equal spacing, consistent with [9]. The bottom chiplets are connected to the interposer through the -bumps surrounded by a capillary underfill material, as detailed in Figure 1(b). The lid contacts only the top chiplet layer through a thermal interface material.
V-B Thermal RC Model Configuration
The number of nodes in the thermal RC network determines the model complexity, runtime, and granularity at which temperature can be observed in the model. A higher node density is used in chiplets to optimize this trade-off, while fewer nodes are used in non-chiplet components, such as the interposer, lid, substrate, and so on. Each chiplet is divided into four equal quadrants. One node is placed within each quadrant to allow for granular temperature monitoring across each chiplet. For non-chiplet layers in each model, an alternate node density is used for each model as described below. This easily configurable non-uniform node density enables higher thermal resolution in critical parts such as chiplets while decreasing the runtime with lower resolution in less critical structures such as the substrate and lid. The DSS models in our experimentation are created by discretizing the thermal RC models with sampling period. The sampling time can be chosen as a function of the application requirements.
2.5D Thermal RC Model Specifics: For the 2.5D systems, the choice of 4 nodes per chiplet leads to 64, 144, and 256 nodes in the chiplet layer of the 16, 36, and 64 chiplet systems, respectively. For all other layers, the number of nodes is equal to the total number of chiplets per layer. This allows the model to maintain higher thermal resolution in the critical chiplet layers while maintaining a fast execution time.

3D Thermal RC Model Specifics: The node densities in the 3D system are adjusted similar to the 2.5D models. The layers that contain chiplets use a 88 grid, implying 4 nodes per chiplet. All other layers have a 44 grid, leading to a lower node density. The entire 3D system consists of 48 chiplets in total. There are a total of 192 nodes counting all nodes within chiplets.
V-B1 Input Workloads and Power Consumption
Identical workloads are considered for the 2.5D and 3D systems, with differences in chiplet power density detailed in the following subsections. The target chiplet systems are analyzed under one synthetic (WL1) and five real AI/ML application workloads (WL2-WL6). The synthetic workload starts with a stress test that applies the maximum power to all chiplets to increase temperature beyond 100∘C. Then, a pseudo-random bit sequence (PRBS) is applied to each chiplet to emulate a wide range of dynamic variations. Finally, all chiplets are turned off to let the temperature return to the ambient state, as depicted in Figure 10. Besides testing transient and steady-state behaviors, this power profile helps us to tune the thermal RC model.
The remaining scenarios consider processing-in-memory (PIM)-based chiplets for accelerating ML workloads. The computational platform is resistive random access memory (ReRAM) based chiplets commonly used in literature [20, 4, 48]. We select this configuration due to it’s ability to efficiently implement matrix-vector multiplication, which is the predominant operation in any CNN workload. Each workload consists of a series of deep neural networks (DNNs) which run in series on the system. The workloads are listed in Table VI. The neural networks (NN) in these workloads consist of several networks such as ResNets, DenseNets, and VGG networks. For example, WL1 contains 16 ResNet34’s, followed by one VGG19, then 5 ResNet50’s, and so on. Each workload contains from 20 to 40 individual networks. Workloads are mapped to the system as computing resources become available, meaning a new NN is mapped to chiplets when it completes the execution of a previous NN. Consequently, these workloads consist of NNs ranging from small NNs like ResNet18, which can be mapped to a single chiplet, to larger NNs such as DenseNet169, which are spread across multiple chiplets.
Workload | Composition |
---|---|
WL1 | Synthetic (see Figure 10) |
WL2 | 16ResNet34 (C), 1VGG19 (C), 5ResNet50 (C), 3DenseNet40 (C), 1ResNet152 (C), 1VGG19 (I), 4 ResNet34 (I), 1ResNet18 (I), 1ResNet50 (I), 1VGG16 (I) |
WL3 | 16ResNet34 (I), 1VGG19 (I), 5ResNet50 (I), 3DenseNet169 (I), 1ResNet110, 1VGG19 (I), 4ResNet101 (I), 1xResNet152 (I), 1ResNet18 (I), 1ResNet50 (I), 1Resnet152 (I) |
WL4 | 16ResNet34 (C), 2VGG19 (I), 4DenseNet169 (I), 3DenseNet40 (C), 5ResNet50 (C), 3ResNet101, 7ResNet150 (I), 2VGG19 (I), 4ResNet101, 1VGG19 (C) |
WL5 | 16Resnet34 (I), 1ResNet152 (I), 1ResNet110 (I), 3ResNet101 (I), 9DenseNet169 (I), 4ResNet34 (I), 12ResNet18 (I), 5ResNet50 (I), 1ResNet152 (I) |
WL6 | 3DenseNet169 (I), 4ResNet34 (I), 12ResNet18 (I), 4ResNet101 (I), 2VGG19 (I), 4ResNet101 (I), 1VGG19 (C), 3DenseNet40 (C) |
After mapping the group of NNs to the target chiplet-based systems, the chiplet power consumption is estimated in two parts, communication and computation. We estimate computation power through NeuroSim and interconnection network power using BookSim [49, 50]. We use running average power throughout the workload execution (40-55 seconds), consistent with power measuring tools such as Intel RAPL [51] and pyNVML [52].
Differences in 2.5D and 3D system chiplet power: The experiments use different hardware parameters, such as voltage and frequency, for the 2.5D and 3D systems. This results in lower per-chiplet power consumption in the 3D system of 1.2W as compared to 3W for the 2.5D system, detailed under the Power section of Table V. Using these parameters, the total system power per lid area of the 3D system is between that of the 36 and 64 chiplet 2.5D system. This level means that the temperature of individual chiplets should be roughly equivalent between these systems, which is confirmed in Figure 10.
V-B2 HotSpot [15] configuration:
We also compare our proposed models to the state-of-the-art tool HotSpot [15] for all the system sizes and workload configurations. Since HotSpot was originally designed for 2D chips, we utilize an extension that adds 3D modeling capabilities [53] to model both 2.5D and 3D integrated systems. Geometry and material parameters are set to be identical to our reference FEM model. Since HotSpot does not support thermal conductivity variations in x-y-z directions, we use the average conductivity for anisotropic material layers (ex. C4 bump layer) in the chiplet package. HotSpot also lacks the support for varying grid sizes across different layers. Therefore, we maintain a uniform grid size matching our chiplet layer.
V-C Execution Time Evaluation
This section evaluates the execution time of the proposed multi-fidelity thermal model set. All simulations are run on a dual Intel Xeon Gold 6242R system with 40 processing cores. We use WL1 for our timing analysis since the execution time is comparable across all workloads.
2.5D Evaluation: Abstracted FEM simulations take 2.4, 14.5, and 38.0 hours for 16, 36, and 64 chiplet systems, respectively. While providing an accurate reference, these long simulation times and significant development effort make FEM impractical for DSE. Our thermal RC models fill this gap with execution times ranging from 53.0 to 1.8 seconds for 16, 36, and 64 chiplets, as summarized in the first 3 systems in Figure 8. Coupled with the accuracy presented in the previous subsection, the 46 to 136-fold speedup demonstrates their viability as a DSE tool.
Thermal RC models are derived directly from the underlying geometry and material parameters, meaning they can be reconfigured for different hardware and design configurations without re-calibration from FEM simulations. Relaxing this physical system to model connection, our DSS models reduce execution time to 39, 96, and 944 ms for 16, 36, and 64 chiplets respectively. This speedup with respect to the RC model enables runtime temperature prediction which can inform dynamic thermal power management (DTPM) decisions to increase system performance and reliability [54]. While maintaining the accuracy for a given configuration, DSS models need to be regenerated if the sampling period or hardware configuration changes.
3D Evaluation: The execution time results of the 3D system are summarized in the far right system of Figure 8. FEM simulations take approximately 3.3 hours for the single 3D system. The thermal RC model dramatically decreases this runtime to 6 seconds. Similar to the results seen for the 2.5D system, the 3D DSS model again shows a dramatically reduced runtime of 0.07 seconds. For comparison, the execution time of a similarly sized 2.5D system DSS model is 0.09 seconds.
Execution time comparison to HotSpot [15]: The commonly used thermal modeling tool HotSpot belongs to the same class as our thermal RC models. The execution times of the proposed models are significantly faster (1862 for 16, 607 for 36, and 245 for 64 - 2.5D integrated chiplet systems while 817 for the 16x3 - 3D integrated chiplet system) than HotSpot, as shown in Figure 8.
The significant speedup mentioned above with similar or higher accuracy is primarily attributed to two factors. First, we employ a non-uniform grid for different layers, as explained in Section IV-C. The speedup due to the use of a non-uniform grid size is 13, 17, 19 and 7 faster execution for 16, 36, 64 - 2.5D integrated and 16x3 - 3D integrated chiplet systems with respect to HotSpot. Second, we employ the adaptive solver LSODA. This solver requires fewer iterations per time step for convergence in comparison to HotSpot. Utilizing an identical grid configuration to HotSpot, the use of this solver alone leads to speedups of approximately 144, 35, 13, and 122, again with respect to the baseline HotSpot model execution time. Finally, we emphasize that MFIT, our multi-fidelity thermal model set covers a much wider range of accuracy and execution time trade-offs than a specific point solution such as HotSpot.

V-D Validation of Thermal RC and DSS model




We validate the accuracy of our thermal RC and DSS models by comparing their temperature estimates to full-system FEM simulation results for the same workload and system configurations. This comparison is completed for each of the three 2.5D system sizes and the single 3D system. In addition to the visualization of the temperature estimate over time, two metrics are used to quantify the accuracy of our thermal RC and DSS models against the FEM results. The MAE metric measures the mean absolute error in temperature across the entire simulation duration. Predicting temperature violations (e.g., tracking the time steps when the temperature exceeds the allowed threshold) is often used by DTPM algorithms. Therefore, the second metric measures the accuracy of our models in predicting temperature violations. We set 85∘C as the maximum allowable temperature threshold for each system without loss of generality [55]. This metric first identifies the time steps in FEM simulations where temperature violations occur (temperature exceeds 85∘C). Then, it computes the percentage of these violations captured by the thermal RC and DSS models (e.g., 100% means all violations are detected with perfect accuracy). The proposed models conservatively flag violations within one degree of the above-mentioned threshold temperature.
To assist users in visualizing the thermal behavior of the system under test, the RC model also creates a heat map of each layer in the system. As an example, the heat map of the interposer layer of a 2.5D 64 chiplet system is shown in Figure 9. This figure shows the temperature gradient that occurs between the center of the interposer, where the heat producing chiplets are located, and the edges of the system, where there are no chiplets. These maps allow for quick visual verification of the system behavior instead of relying purely on numerical results.
2.5D Validation Results: Figures 10(a), 10(b), and 10(c) plot the temperature as a function of time for each 2.5D system size of a representative chiplet while running workload WL1. All three plots of 2.5D systems clearly show that the systematically constructed thermal RC and DSS models produce near-identical results to the FEM baseline. They closely follow the FEM results during the stress test (temperature increases until reaching the maximum point), randomly changing chiplet power consumption (middle portion), and cool-down periods.
2.5D - 16 Chiplets | 2.5D - 36 Chiplets | 2.5D - 64 Chiplets | 3D - 16x3 Chiplets | ||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Workload | Model | MAE (∘C) |
|
MAE (∘C) |
|
MAE (∘C) |
|
MAE (∘C) |
|
||||||||
WL1 | Thermal RC | 1.23 | 93.4 | 1.42 | 96.9 | 1.17 | 99.2 | 0.82 | 99.7 | ||||||||
DSS | 1.23 | 93.4 | 1.42 | 96.9 | 1.17 | 99.2 | 0.82 | 99.7 | |||||||||
HotSpot | 2.74 | 67.7 | 1.64 | 96.9 | 1.69 | 98.1 | 1.32 | 94.5 | |||||||||
WL2 | Thermal RC | 0.86 | 95.9 | 1.16 | 100 | 1.08 | 100 | 1.08 | 100 | ||||||||
DSS | 0.86 | 95.9 | 1.16 | 100 | 1.08 | 100 | 1.08 | 100 | |||||||||
HotSpot | 1.57 | 75.0 | 1.24 | 100 | 1.19 | 100 | 1.19 | 100 | |||||||||
WL3 | Thermal RC | 1.02 | 100 | 1.28 | 77.2 | 1.17 | 89.3 | 1.05 | 100 | ||||||||
DSS | 1.02 | 100 | 1.28 | 77.2 | 1.17 | 89.3 | 1.05 | 100 | |||||||||
HotSpot | 1.97 | 100 | 1.18 | 42.3 | 1.33 | 74.4 | 1.08 | 100 | |||||||||
WL4 | Thermal RC | 1.41 | 96.6 | 1.63 | 95.5 | 1.55 | 97.6 | 1.30 | 99.3 | ||||||||
DSS | 1.41 | 96.6 | 1.63 | 95.5 | 1.55 | 97.6 | 1.30 | 99.3 | |||||||||
HotSpot | 2.29 | 95.6 | 1.89 | 92.0 | 2.15 | 97.7 | 1.85 | 98.0 | |||||||||
WL5 | Thermal RC | 1.01 | 100 | 1.25 | 87.8 | 1.07 | 82.4 | 1.03 | 100 | ||||||||
DSS | 1.01 | 100 | 1.25 | 87.8 | 1.07 | 82.4 | 1.03 | 100 | |||||||||
HotSpot | 1.94 | 100 | 1.16 | 60.7 | 1.40 | 52.9 | 1.05 | 100 | |||||||||
WL6 | Thermal RC | 0.89 | 98.1 | 1.30 | 84.8 | 1.21 | 90.9 | 1.11 | 98.3 | ||||||||
DSS | 0.89 | 98.1 | 1.30 | 84.8 | 1.21 | 90.9 | 1.11 | 98.3 | |||||||||
HotSpot | 1.62 | 85.8 | 1.28 | 89.7 | 1.56 | 89.5 | 1.24 | 86.7 |
The first 3 columns of Table VII summarize the accuracy results for all 2.5D systems and workloads. The worst-case mean absolute errors are only 1.41, 1.63, and 1.55 degrees (highlighted in dark red) for 16, 36, and 64 chiplet systems, respectively. These results indicate that the proposed models achieve excellent accuracy across different hardware configurations and workloads. Our models also achieve high accuracy in predicting temperature violations. For example, the worst-case accuracy for the 16-chiplet system is 93.4% (i.e., only 6.6% of the time steps where violations are missed) for WL1. Our models capture 100% of the violations during WL3 and WL6 while missing a handful of them for other workloads. The corresponding accuracy for the 36-chiplet system is above 95% for WL1, WL2, and WL4. We observe 77.2%, 84.8%, and 87.8% accuracy for WL3, WL6, and WL5, respectively. These relatively lower accuracy values stem from sudden temperature spikes that lead to short-term temperature violations in these workload-system combinations. Temperature spikes in specific chiplets occur when several grouped chiplets experience a transient power spike simultaneously. This increases the temperature of the more central chiplets in the group. In these cases, the peak temperatures are mostly at or below 85 degrees with infrequent short-term violations, which can be tolerated. For example, FEM simulations indicate only 255 temperature violations across all chiplets in WL3 compared to 11 thousand violations in WL1. Hence, missing even a few violations impacts the accuracy heavily when the RC and DSS models do not capture these spikes. In contrast, our thermal RC and DSS models effectively detect more prolonged violations, as evidenced by WL1, WL3, and WL4. Similarly, our thermal RC and DSS models achieve high accuracy for the 64-chiplet system, as shown in Table VII. The lowest accuracies are 82.4% for WL5 and 89.3% for WL3, which have few total violations.
3D Validation Results: Figure 10(d) plots the temperature as a function of time for the single 3D system of a representative chiplet running WL1. The plot shows similar behavior to the 2.5D comparison, where the RC and DSS match each other exactly and match the reference FEM results extremely closely during the stress test, random, and cool-down portions of the workload.
The far right column of Table VII summarizes the accuracy results for the single 3D system for each workload. The worst-case MAE is only 1.3 degrees (highlighted again in dark red). This result shows that the proposed models maintain high levels of accuracy even when applied to a stacked die package. This high degree of accuracy is repeated when predicting temperature violations. The worst case temperature violation prediction accuracy is only 98.3%, occurring for workload 6.
Accuracy comparison to HotSpot [15]: Table VII also lists the MAE of HotSpot simulations compared to FEM simulations for 2.5D and the 3D system. For the 2.5D system results, the average error of HotSpot is 0.95, 0.05, and 0.35 degrees greater than our thermal RC and DSS models for the 16, 36, and 64 chiplet systems, respectively. Notably, HotSpot also has lower accuracy in detecting temperature violations, but our primary advantage is in execution time, as discussed in Section V-C. For the 3D results, HotSpot’s average error is 0.22 degrees greater than that of our thermal RC and DSS models. HotSpot again shows lower accuracy in detecting temperature violations in workloads 1, 4, and 6. The larger error across system configurations can be attributed to the tuning of thermal RC model parameters based on the available reference FEM thermal model results. Additionally, HotSpot does not include the ability to provide different thermal conductivities along the x, y, and z-axis, further decreasing accuracy.
VI Conclusion
Conventional monolithic 2D chips cannot sustain the increasing performance and compute capacity demands due to increasing manufacturing costs. 2.5D and 3D multi-chiplet systems have emerged as cost-effective solutions to continue the required scaling. However, substantial compute power in a small volume intensifies the power density, leading to severe heat dissipation and thermal challenges. There is a strong need for open-source thermal modeling tools that enable researchers to analyze thermal behavior and perform thermally-aware optimizations. Re-purposing existing approaches developed for monolithic chips incurs accuracy and execution time penalties, while custom-designed singular solutions have limited scope. To fill this gap, this paper proposed MFIT, a set of multi-fidelity thermal models that span a wide range of accuracy and execution time trade-offs. Since the proposed models are consistent by construction, designers can use them throughout the design cycle, from system specification to design space exploration and runtime resource management.
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